Intel CEO Lip-Bu Tan (Image Source: Intel)
AsianFin -- Following TSMC’s announcement of progress on its 1.8nm technology on April 24, Intel has revealed major updates to its Intel Foundry Services roadmap, signaling a deepening competition in next-generation semiconductor manufacturing.
Speaking at the 2025 Intel Foundry Conference in San Jose, California on April 29, Intel CEO Lip-Bu Tan announced that the company’s Intel 18A (1.8nm-class) process has officially entered the risk production phase. The Fab 52 facility in Arizona has already completed the tape-out for Intel 18A and is on track to begin full-scale mass production later this year.
Intel also introduced several new process iterations, including Intel 18A-P, Intel 18A-PT, and its most advanced node to date—Intel 14A, a 1.4nm-class technology. The company expects these next-generation nodes to deliver a 15%–20% improvement in performance per watt over the standard 18A process. Intel aims to roll out products based on the 14A node around 2027.
“I will ensure the success of our foundry business.” Tan emphasized the importance of customer-centricity, pledging to listen to client feedback, enhance Intel’s product offerings, and partner closely with the U.S. government to build what he called a “great American foundry.”
His remarks follow mounting speculation that Intel might divest its foundry unit following recent leadership changes. Tan’s public statement serves as a direct rebuttal to those rumors and signals Intel’s long-term commitment to competing at the forefront of global semiconductor manufacturing.
Meanwhile, Taiwan Semiconductor Manufacturing Company (TSMC) continues to push its own technology roadmap. In April, the company confirmed that its 2nm (N2) process will enter mass production in the second half of 2025. TSMC also revealed that its 1.4nm-class A14 process is scheduled for mass production by 2028, with an enhanced A14 SPR version to follow in 2029.
These timelines set up a new flashpoint in the race between Intel and TSMC, with 2028 expected to mark a pivotal moment in the battle for 1.8nm supremacy. Both firms are vying to outpace Samsung, which has struggled with yield issues in its advanced process nodes.
While the world’s leading chipmakers push forward on bleeding-edge technology, China’s major foundries such as SMIC and Huahong remain focused on mature nodes—primarily 28nm and above. Only a handful of their lines currently produce 16/12nm chips. IDC forecasts that China’s mature-node chip production will account for 28% of global capacity by 2025, while SEMI predicts that share could rise to 39% by 2027.
This raises a strategic question: should China pursue advanced process technology like TSMC and Intel?
According to Professor Wei Shaojun of Tsinghua University, who chairs the Integrated Circuit Design Branch of the China Semiconductor Industry Association, the answer lies in pivoting away from conventional paths. He argues that with external constraints limiting access to advanced manufacturing equipment and IP, Chinese firms should shift focus toward design-driven innovation—leveraging architecture and microsystem integration rather than chasing smaller nodes. “The key is to break path dependency and establish a technological framework with Chinese characteristics,” Wei said.
The financial burden of chip innovation is also becoming unsustainable. Handel Jones, CEO of International Business Strategies (IBS), estimates the average design cost for a 28nm chip is around $40 million. That figure balloons to $217 million at 7nm, $416 million at 5nm, and $590 million at 3nm. All-in development costs for a 3nm chip can approach $1 billion, driven by expensive wafer runs, EUV lithography equipment, and low initial yields.
Looking ahead, the cost to develop a 2nm chip could exceed $725 million, potentially surpassing even 3nm due to higher R&D, equipment, and process complexity.
Despite these rising costs, the return on performance, power efficiency, and chip area (PPA) is slowing. For example, Qualcomm’s Snapdragon 8s Gen 4, built on a 4nm node, delivers a 31% CPU boost and 49% GPU performance increase—with energy efficiency up 39%. Intel’s Core Ultra 7 165H, built on its newest process with chiplet integration, offers just an 8% improvement in performance per watt over the previous 10nm Core i7-1370P.
Despite the enormous investments required to push chip manufacturing to more advanced nodes, the performance gains—particularly in CPU capabilities—have been increasingly underwhelming. Industry observers note that the cost-performance tradeoff has become harder to justify. This trend is underscored by NVIDIA CEO Jensen Huang, who is now placing greater emphasis on the surging demand for AI model tokens and the strategic role of the company’s latest B200 chip in the evolving AI landscape.
A semiconductor insider told TMTPost that domestic Chinese chipmakers are right to avoid chasing leading-edge process technologies. “Beyond 12nm, the impact of further process shrinking on overall performance becomes marginal,” the person said, adding that innovation should instead focus on design, system integration, and architecture.
Still, as the global chip race pushes toward the 1.8nm era, both Intel and TSMC are pursuing new breakthroughs aimed at achieving meaningful improvements in PPA—power efficiency, performance, and area.
Intel, for its part, has taken a bold step by scrapping plans for mass production of its 20A node and moving directly to Intel 18A, equivalent to 1.8nm. Intel 18A is the first process node in the industry to combine PowerVia—its backside power delivery network (BSPDN)—with RibbonFET, a next-generation gate-all-around (GAA) transistor architecture.
PowerVia relocates power delivery to the backside of the chip, enhancing performance and enabling higher transistor density. Intel claims this boosts ISO power efficiency by 4% and increases standard cell utilization by 5% to 10%. RibbonFET, meanwhile, uses four vertically stacked nanosheets fully surrounded by gates, delivering faster switching speeds and greater density in a smaller footprint.
The high-volume manufacturing (HVM) timeline for Intel 18A is expected to roughly coincide with TSMC’s 2nm N2 node, setting the stage for a new round of competition at the cutting edge of semiconductor innovation.